1. Field of the Invention
The embodiments of the invention generally relate to semiconductor transistors and more particularly relate to a dual mask method that forms a shallow well region and a deep well region within transistors, and the resulting structure.
2. Description of the Related Art
Complimentary metal oxide semiconductor (CMOS) transistors utilize transistors that have opposite characteristics depending upon the dopants used. These opposite type transistors are commonly referred to as positive-type (P-type) and negative-type (N-type) transistors.
One issue that exists with such transistors as they are scaled (reduced in size) relates to the spacing between the P-type and N-type transistors. More specifically, as the transistors becomes smaller and smaller, it becomes more difficult to separate the well regions of the different types of transistors. The embodiments described below address this situation using a new methodology that produces a new structure.